Technical brief


技术简介

Technical Introduction


The self-developed substrate fan-out packaging technology of the "New Type Special Integrated Circuit Packaging Base Project" by Hefei Smat Technology Co., Ltd. is an advanced packaging technology that achieves high precision interconnections through the use of large-sized square carrier boards. This technology enables the high-density restructuring of chips, epoxy resin encapsulation, the use of RDL re-routing process to overcome I/O limitations, and the combination of the scale effect of square panels with the process routes compatible with PCB for chip packaging, thus forming a technological closed loop of "innovation in carrier structure → innovation in interconnection → optimization in cost."

As the first domestic company to complete the mass production of a substrate fan-out type packaging and testing production line, Smat's substrate fan-shaped packaging technology can achieve more efficient interconnections, more flexible chiplet configurations, higher integration levels, better heat dissipation performance, and superior cost competitiveness. It is the most economical and effective packaging technology solution for achieving large size, high density, high integration, and cost-effective performance.

视频标题

Process Flow


Currently, the silicon-based technology substrate fan-out packaging process is illustrated in the figure. after the chip is ground and scored, it is re-arranged using a chip mounting technique. Through a multi-layer re-routing process, the circuitry is created, and the chip's terminals are fan-out and interconnected. Then, external pin routing is completed, and chemical tinning is performed. The chip is cut to shape, and the final product is manufactured.

Technical Introduction

Core Sites


The current process flow for Smat's substrate fan-out type packaging is as follows: after the chip is ground and scored, it is re-arranged using a chip mounting technique. Through a multi-layer re-routing process, the circuitry is created, and the chip's terminals are fan-out and interconnected. Then, external pin routing is completed, and chemical tinning is performed. The chip is cut to shape, and the final product is manufactured.


Bumping

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DOF Die Attaching

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DOF Molding

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Panel Grinding

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Plating

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E’less Sn

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Package Saw

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Technological Superiority


Low-profile resistors with low parasitic inductance

High design flexibility meets customers' customized needs

Reduce package size, enhance product performance

Technological Advantages

Good thermal and electrical conductivity

Dual-sided multi-layer RDL capability, with strong packaging scalability

No LF solution—shorten the new product development cycle.